The present invention is generally drawn to a pulse width modulation receiver.
Interfaces used for inter/intra-device communication in a chip run in two modes: 1) high-performance and hence high-power mode: and 2) low-performance and hence low-power mode. One of the low-power modes is a pulse width modulation (PWM) mode, where the data information is hidden in the duty-cycle and the clock information is hidden in the period. In the PWM mode, there is no separate external clock available to save power.
FIG. 1 illustrates an electronic device 100 that uses PWM signals for internal communication.
As shown in the figure, electronic device 100 includes a component 102, a component 104 and a component 106. Component 102 is operable to transmit a PWM signal 112 to component 104 via a communication channel 108. Component 104 and component 106 are operable to send signals 114 to one another is a communication channel 110. As used herein, a communication channel is any channel that is able to transmit a PWM signal, non-limiting examples of which include a wired channel and wireless channel.
M-PHY is a mobile-telephone technology standard that uses PWM inter/intra-device communication. Some of the M-PHY constraints include: no external clock being available; valid data should be at the end of the bit (i.e., the output of the nth bit should be available in the (n+1)th bit); and the input of the PWM signal is a low voltage differential signal. A low-power PWM signal for inter/intra-device communication in a chip will now be further described with reference to FIG. 2.
FIG. 2 illustrates differential PWM signal 112 and its corresponding data output 200 and clock output 202.
As shown in the figure, PWM signal 112 includes a positive differential signal 204, a negative differential signal 206 and a common mode signal 208. PWM signal 112 further includes an nth bit 210 and a (n+1)th bit 212. Bit 210 has a TL portion 214 and a TH portion 216. Bit 212 has a TL portion 218 and a TH portion 220.
PWM signal 112 has a period that is the length of one bit. However, the duty cycle of each bit may vary in accordance with the data therein. In particular, the duty cycle of bit 210 is the ratio of TH portion 216 to TL portion 214, whereas the duty cycle of bit 212 is the ratio of TH portion 220 to TL portion 218.
When demodulated by a PWM receiver (not shown), PWM signal 112 may be broken into data output 200 and clock output 202. Further, data output 200 includes an output bit 222 and an output bit 224 and clock output 202 includes a plurality of pulses.
The value of a bit in data output 200 is based on the duty cycle of the corresponding bit in PWM signal 112. If the TH portion of a bit is larger than the TL portion of that bit, then the corresponding bit in the data output is a 1. In this example, TH portion 216>TL portion 214. Therefore the value of corresponding output bit 222 is 1. Alternately, if the TL portion of a bit is larger than the TH portion of that bit, then the corresponding bit in the data output is a 0. In this example, TL portion 218>TH portion 220. Therefore the value of corresponding output bit 224 is 0.
One main problem associated with receiving and demodulating a low-power PWM mode signal is that no reference clock is available. One conventional method to address this issue is by using a PWM receiver that includes a phase lock loop. This will be described with reference to FIG. 3.
FIG. 3 illustrates a conventional PWM receiver 300.
As shown in the figure, conventional PWM receiver 300 includes a phase lock loop (PLL) 302 and a demodulator 304.
PLL 302 is arranged to receive a PWM signal 306 and output a plurality of signals 308. Demodulator 304 is arranged to receive the plurality of signals 308 and to output a plurality of bits and a clock signal, all of which are indicated by 310.
The implementation using PLL 302 consists of over-sampling the high time (TH) and low time (TL) using the PLL clock of a frequency, Fclk, as follows:Fclk>(Finput/minimum duty−cycle).  (1)
An example of TH and TL will be described with reference to FIG. 4.
FIG. 4 illustrates an example PWM signal 306.
As shown in the figure, PWM signal 306 includes a bit 402 and a bit 404. PWM signal 306 is illustrated as a non-differential signal to simplify the discussion. It should be noted that some conventional PWM receivers similar to conventional. PWM receiver 300 use differential signals and others use non-differential signals. Bit 402 has a TL portion 406 and a TH portion 408. Bit 404 has a TL portion 410 and a TH portion 412.
Returning to FIG. 3, in operation, PLL 302 may sample PWM signal 306 at a much higher frequency than the frequency of PWM signal 306. For purposes of discussion, presume that while sampling PWM signal 306, PLL 302 will obtain 100 consecutive low values associated with TL 406 and will obtain 300 consecutive high values associated with TH 408. These sampled values may be passed to demodulator 304 via plurality of signals 308. Demodulator 304 may then determine, among other things outside the scope of this discussion, the duty cycle of PWM signal 306 based on the ratio of sampled low values and sampled high values.
Setting the frequency of the clock of PLL 302 in accordance with equation (1) will yield at least one sample of signal 306 per high/low time. This is a theoretical/ideal implementation. However, to be practically feasible, Fclk, should be as follows:Fclk>3(Finput/minimum duty−cycle),  (2)
Setting the frequency of the clock of PLL 302 in accordance with equation (2) will account for false sampling at the two edges of high/low duration. In any event, the samples are stored in a counter and a digital comparator to give out data based on the high/low samples. This data is shown at plurality of signals 308. As the input frequency increases, PLL 302 needs to use a higher frequency clock, which means higher current consumption. For example, PLL 302 may operate at ˜2 mA for 2 GHz, an implementation of which contradicts the very meaning of transmitting/receiving in PWM mode. Therefore digital implementation becomes power hungry at higher frequencies.
Another problem is that the input frequency can vary up to a factor of three within an operation mode, and there are different operating frequencies based on different modes of operation, referred to as gears in the M-PHY specification. For example: in the first gear, the frequency range of support is from 3 MHz-9 MHz; in the first gear, the frequency range of support is from 6 MHz-18 MHz; in the third gear, the frequency range of support is from 12 MHz-36 MHz; in the fourth gear, the frequency range of support is from 24 MHz-72 MHz; and in the fifth gear, the frequency range of support is from 48 MHz-144 MHz.
Conventional systems for addressing the problem above include designing a circuit for operation at the highest frequency and expecting the circuit to work for lowest frequency without consuming extra power. Once such system includes a delay cell based implementation, for lower frequency within a gear the number of delay cells traversed. This will be described in greater detail with reference to FIG. 5
FIG. 5 illustrates another conventional PWM receiver 500.
As shown in the figure, conventional PWM receiver 500 includes a plurality of delay cells 502 and a latch comparator 504. The plurality of delay cells 502 are arranged to receive a PWM signal 506. PWM signal 506 then circulates through the plurality of delay cells 502 in a direction indicated by arrow 508 and are output to latch comparator 504. Latch comparator 504 is arranged to output a data signal 510.
In operation, whenever the value of PWM signal 506 is low, it is passed in the direction of arrow 508. For example, suppose PWM 506 starts with a negative edge. Whenever there is a negative edge, PWM 506 passes in the forward direction, from the first delay element to the second delay element, etc. As soon as there is a rising edge at the input, PWM 506 moves in the opposite direction and latch comparator 504 latches PWM 506 directly.
For purposes of discussion, consider the situation where PWM 506 as an input duty cycle of 40-60, i.e., 40% low and 60% high. For 40% of the input (when it is low), PWM 506 will flow in the forward direction and it will then reverse, path after 40%. At 80% of the period (assuming the forward and the reverse path delays are the same), latch comparator 504 will latch PWM 506 which was high at the time.
Any digital scheme based on delay lines, will require calibration or trim to support large frequency range of operation (as required by M-PHY standard). Delay variation across process, voltage and temperate is on the order of a factor of three (X3). Due to large variation in delay cells, analog schemes are attractive. The conventional analog scheme is based on charge-pump with charging and discharging currents. Output can be compared to a known reference (close to ground) using a comparator. This circuit performance is limited by the positive and negative differential input current mismatches and also on the accuracy of the voltage reference. As such, these types of conventional circuits consume lower power but this will occupy more area compared to a digital implementation.
What is needed is a low power PWM receiver that operates at a low power without taking up large amounts of real estate.